FIG. 6 illustrates an example of basic configuration for testing a bit error rate of a signal pattern by using a bit error rate measurement apparatus. When measuring a bit error rate of a device under test 74, the device under test 74 receives a test pattern 72 and a clock 73 from a pattern generator 71. A bit error measurement apparatus 75 is provided with a signal 61 to be measured and a clock 60 which are output from the device under test 74 to perform a bit error measurement. In a situation like this, it is required that the test pattern 72 and a test pattern generated by the test pattern generator in the bit error measurement apparatus 75 must be the same pattern data.
In executing the bit error test in a critical condition such as an ultra high speed, 10 GHz for example, the likelihood of error in a serial pattern signal in the device under test 74 will increase. The bit error rate measurement apparatus of the present invention is to analyze such pattern conditions which cause a bit error rate.
FIG. 7a shows a block diagram of a conventional bit error measurement apparatus to explain the procedure of bit error measurement. The bit error measurement apparatus comprises a demultiplexer 64, a test pattern generator 62, a demultiplexer 63, a verifier 65, an error counter 70, and a pattern synchronizing part 66. The pattern synchronizing part 66 includes a synchronization detecting counter 66a, a threshold register 66b, and a comparator 66c. The pattern synchronizing part 66 synchronizes a signal pattern 61 to be measured with a test pattern generated by the test pattern generator 62.
Demultiplexer 63 and 64 are to convert an ultra high speed serial input signal into parallel data. In this embodiment, the serial input signal is converted to 16 bit-parallel low speed signals 63a and 64a, which make the following circuits feasible to be formed with high or middle speed ECL devices.
Pattern synchronization considered here means that even if an unknown signal 61 to be measured has some errors, and if a rate of such errors is lower than a specified rate set by a threshold register 66b, it is considered as synchronous. The synchronization detection counter 66a counts the bit error number for every predetermined time period. After the predetermined time period, a bit error number greater than a specified number is detected by comparing the counted value with a value stored in the threshold register 66b, and a pulse signal 67 is generated by a comparator 66c for masking the clock signal 60.
The test pattern generator 62 receives the clock mask signal 67 and outputs the next test pattern by delaying the output phase of a test pattern 62a by one bit of clock signal 60. This timing delay operation is repeated until the synchronization between the test pattern 62a and the signal 61 to be measured is reached. When the measuring signal 61 is synchronized with the test pattern 62a, the clock mask signal 67 from the comparator 66c becomes inactive.
The above-mentioned operation is a preliminary procedure for a bit error measurement. After reaching the synchronous state as above, the test pattern 62a is generated in synchronism with the measuring signal 61 throughout the test as a reference pattern. The bit error rate measurement proceeds under this situation as described below.
Because of 16 bits parallel operation of the error counter 70 in this example, the error bit number of a bit error detection signal 65a can be 0-16. After converting this plural error bit numbers into binary 5 bits, the error detection signal is added to the contents in the error counter 70. The counted value is stored in the error counter 70 to fulfill the bit error count function. In order to calculate the bit error rate, this error count value is read by a controller CPU every predetermined time interval. The error rate is calculated based on the error count value and the predetermined time period and the final test result is output by, for example, a display.
In FIG. 7a, the above explanation is made for the configuration where the verifier 65 receives the parallel data converted by demultiplexer 63 and 64. On the other hand, as shown in FIG. 7b, there is another example of configuration in which the synchronization and the error count are accomplished by providing serial data directly to the verifier 65 and providing a bit error detection signal 65d of one bit to the error counter 70 and the pattern synchronizing part 66.
As explained above, since the conventional bit error measurement apparatus obtains the error rate data solely from the error counter 70, it is difficult to specifically analyze, investigate or identify causes of errors in a signal under measurement. To specify such causes of errors in a signal under test, the measurement have to be repeated after modifying the contents of a test pattern to be generated by the pattern generator 71 and test pattern generator 62 to see whether the bit error rate will increase and/or decrease. From this result, the pattern conditions which are the cause of increase or decrease in bit error rates could be identified.
As has been foregoing, in the conventional measurement apparatus, although the error rate can be obtained by means of the error counter 70, it is necessary to modify the test pattern, repeat the measurement plural times and compare these results in order to specify the pattern conditions which cause the occurrence of error rate. Thus, the conventional bit error rate measurement apparatus is inconvenient and cumbersome for fully analyzing the cause of error in the signal under test. Thus, there is a need to provide an improved bit error measurement apparatus.